Quick Explanation
- Experiment with the latency and power impacts on safety critical applications
- Separate I- and D- cache from 4 to 64 KB
- Eight-stage dual-issue pipeline
- Instruction pre-fetch, mispredict/flush and selected dual-issue execution
- Concurrent execution for load-store, MAC, shift-ALU, divide and floating point
- 64-bit AMBA AXI bus master for Level-2 memory and peripheral access
- Supports DMA arbitration
Protocol
- ARM Cortex-R is a f32-bit RISC core, optimized for hard real-time and safety-critical applications. Implements the ARM Real-time (R) profile
