Quick Explanation
- L1 cache 32 KB I, 32 KB D
- L2 cache 128 KB–8 MB
- Out-of-order superscalar execution
- 8-stage pipeline
- NEON SIMD instruction set extension
- VFPv3 floating point unit
- Thumb-2 instruction set
- Multi-core processing
Protocol
- ARM Cortex-A9 MPCore is a 32-bit processor core implementing the ARMv7-A architecture. It is a multicore processor providing up to four cache-coherent cores.
