Quick Explanation
- Supports ARM V8 ISA
- Supports out-of-order pipeline
- Supports 15 stage pipeline
- Supports NpBench's networking task profile
- Supports execution of floating point instruction
- 3-way superscalar execution pipeline
- DSP and NEON SIMD extensions
- VFPv4 Floating Point Unit
- 32 KiB data (2-way set-associative) + 48 KiB instruction (3-way set-associative) L1 cache per core
- Level-2 (16-way set-associative) cache controller, 512 KB to 4 MB configurable size per cluster
- 48-entry translation lookaside buffer (TLB) with support for 4 KB, 64 KB, and 1 MB page sizes
- 32-entry L1 data TLB with native support for 4 KiB, 64 KiB, and 1 MB page sizes
- 1024-entry L2 TLB per core
- Ability to generate mispredict and pipeline flush
- Supports integration with AMBA and standard memory
Protocol
- ARM Cortex-A72 is a microarchitecture implementing the ARMv8-A 64-bit instruction set
