Avoid Million-Dollar Design Mistakes with Early Exploration Date: September 4 2025 Register for Session 1 (APAC): 11:30 AM IST | 2:00 PM CST | 3:00 PM JST/KST: Session1 Register for Session 2 (US): 10:00 AM PST | 1:00 PM EST: Session 2 Speakers Deepak Shankar, Founder, Mirabilis Design Inc. LinkedIn Prakash Sahay, Solutions Group Director, […]
Mirabilis Design Newsletter 2025 Founder’s Note I hope you’re enjoying a wonderful summer! At Mirabilis Design, AI is taking center stage — helping us track dynamic behavior during simulation and detecting performance bottlenecks, thus maximizing the role of system modeling. By integrating VisualSim into the broader EDA workflow through co-simulations and more parameters for system components, we’re […]
A Comprehensive Approach to Power & Performance Optimization Revolutionizing Systems Engineering with VisualSim As the automotive industry transitions into an era dominated by digital and electronic solutions, the design challenges associated with Electronic/Electrical (E/E) architectures have become increasingly complex. From managing latency and power consumption to integrating cutting-edge software and hardware, modern automotive systems demand […]
ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe – Designing the interconnect is not for the weak-hearted! Timings: Session 1: 11:30 AM India / 3:00 PM Japan or Korea / 2:00 PM China Register here: https://bit.ly/4elxVwY Session 2: 10:00 AM PDT / 1:00 PM EDT Register Here: https://bit.ly/4epEQ8v With so many Network-on-Chip (NoC) solutions […]
Methodology for System-level Comparison of ARM vs RISC-V Cores for Latency and Power Consumption System-level analysis is the only methodology to compare the performance and power consumption of two processor architectures. Unfortunately, processor models to perform the comparison are not easily available. This article describes a performance and power comparison methodology using system-level IP between […]
