Avoid Million-Dollar Design Mistakes with Early Exploration Date: September 4 2025 Register for Session 1 (APAC): 11:30 AM IST | 2:00 PM CST | 3:00 PM JST/KST: Session1 Register for Session 2 (US): 10:00 AM PST | 1:00 PM EST: Session 2 Speakers Deepak Shankar, Founder, Mirabilis Design Inc. LinkedIn Prakash Sahay, Solutions Group Director, […]
Mirabilis Design Newsletter 2025 Founder’s Note I hope you’re enjoying a wonderful summer! At Mirabilis Design, AI is taking center stage — helping us track dynamic behavior during simulation and detecting performance bottlenecks, thus maximizing the role of system modeling. By integrating VisualSim into the broader EDA workflow through co-simulations and more parameters for system components, we’re […]
Unlocking Optimal Power and Performance: A Deep Dive into ARM SoC Modeling In the competitive world of semiconductor design, balancing power consumption with high performance is a constant challenge. With VisualSim Architect, engineers can simulate intricate ARM-based SoCs with unparalleled accuracy, paving the way for innovative, power-efficient solutions. The Future of SoC Design: As the […]
Mirabilis Design Accelerates SoC Development with New System-Level IP Library for Cadence Tensilica Processors Mirabilis Design Inc., a leader in system-level IP and simulation solutions, has unveiled a new IP library tailored for Cadence Tensilica processors. This strategic development aims to significantly accelerate System-on-Chip (SoC) design and development processes, offering designers a robust platform for […]
Mirabilis Design Adds System-Level Modelling Support for Industry-Standard Arteris FlexNoC and Ncore Network-on-Chip IPs Mirabilis Design Inc., a leader in system-level modeling and simulation solutions, has announced the integration of support for Arteris FlexNoC and Ncore Network-on-Chip (NoC) IPs into its VisualSim Architect tool. This advancement enables designers to perform early-stage architectural exploration and performance […]
