RISC-V architecture exploration using VisualSim Architect.

Jun 06, 2025  |  Author : admin_mirabilis

Abstract The RISC-V architecture offers unparalleled flexibility in processor design, allowing custom instruction sets, memory hierarchies, and peripheral configurations. This study presents a model-driven approach using VisualSim Architect to explore the performance, power, and functional trade-offs of RISC-V cores in complex system-on-chip (SoC) environments. We simulate multiple RISC-V microarchitectures with configurable pipeline stages, cache hierarchies, […]

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 ARM corelink, Arteris NoC, UCIe, Bunch-of-wires, CXL and PCIe

Oct 02, 2024  |  Author : admin_mirabilis

ARM CoreLink, Arteris NoC, UCIe, Bunch-of-Wires, CXL, and PCIe – Designing the Interconnect is Not for the Weak-Hearted! In today’s high-stakes world of System-on-Chip (SoC) design, figuring out the best interconnect architecture can feel like navigating a maze. With so many choices—ARM CoreLink CMN700, Arteris FlexNoC, UCIe, Bunch-of-Wires, CXL, and PCIe—it’s easy to feel overwhelmed. […]

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Unleashing the Potential of AI in Simulation

Feb 05, 2024  |  Author : admin_mirabilis

Unleashing the Potential of Artificial Intelligence (AI) in Simulation: Revolutionzing Efficiency & Confidence The current technological landscape is saturated with the omnipresence of Artificial Intelligence (AI), Machine Learning (ML), and Neural Networks, raising pertinent questions about the authenticity of their applications. A recent insightful conversation with a client has sparked a profound exploration into the […]

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Webinar: Processing – Turning IoT Data into Intelligence​

Sep 18, 2023  |  Author : admin_mirabilis

In the ever-evolving landscape of the Data Center enabled systems or Internet of Things (IoT), the role of processors has taken centre stage. As the demand for smarter and more efficient IoT devices grows, the careful selection of Edge and Fog computing architectures becomes paramount. Join us for an illuminating webinar that will unravel the […]

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